1. Field of the Invention
The present invention relates to a solid-state image pickup device of a structure having a plurality of image pickup pixels, each provided with a photoelectric transducer, and reading a signal photoelectrically converted and accumulated in the photoelectric transducer out of each image pickup pixel unit using a plurality of transistors. More particularly, the present invention relates to a solid-state image pickup device capable of operating at a lower voltage.
2. Description of the Related Art
Hitherto, a solid-state image pickup device has been proposed in the form of a MOS solid-state image pickup device including photodiodes, which serve as photoelectric transducers and are arranged in a one-to-one relation to image pickup pixels, and various MOS transistors for transferring, selecting, amplifying and resetting photo-charges accumulated in each photodiode.
FIG. 4 is a circuit diagram showing one example of a construction of a conventional pixel unit in such a MOS solid-state image pickup device, and FIG. 5 is a timing chart showing one example of operation of the pixel unit shown in FIG. 4.
The construction shown in FIG. 4 represents a circuit used for outputting photoelectrons accumulated in a photodiode 10 to a vertical signal line 12. The lower end side (i.e., the voltage output to an S/H and CDS circuit described later) of the vertical signal line 12 is held at a high impedance level. The upper end side of the vertical signal line 12 is connected to a constant-current source 14 located outside the pixel unit (image pickup section).
Further, as shown in FIG. 4, four MOS transistors 20, 22, 24 and 26 are disposed around the photodiode (referred to as “PD” hereinafter) 10.
A reset transistor 20 and a transfer transistor 22 are connected between a driving power source (driving voltage Vdd) and an output of the PD 10. A floating diffusion (referred to as “FD” hereinafter) node 16 is provided between a source of the reset transistor 20 and a drain of the transfer transistor 22.
Further, a selection transistor 24 and an amplification transistor 26 are connected between the vertical signal line 12 and the driving power source (driving voltage Vdd). The FD node 16 is connected to a gate of the amplification transistor 26.
A reset pulse is inputted to a gate of the reset transistor 20, a transfer pulse is inputted to a gate of the transfer transistor 22, and a selection pulse is inputted to a gate of the selection transistor 24.
In the circuit construction described above, when the selection transistor 24 is turned on, the amplification transistor 26 and the constant-current source 14 located outside the image pickup section cooperate to establish a source follower connection. Therefore, the potential of the vertical signal line 12 takes a value following the gate voltage of the amplification transistor 26, i.e., the potential at the FD node 16. That value provides an output of the pixel.
A method of driving the conventional pixel unit will be described below with reference to FIG. 5.
First, at the timing of “t10” along the horizontal axis of FIG. 5, photoelectrons are accumulated in the PD 10.
Then, at the timing of “t11”, the selection transistor 24 is turned on.
At the timing of “t12”, a reset pulse is inputted to the reset transistor 20, thereby resetting the FD node 16.
Thereafter, during a period including the timing “t13”, the potential (reset level) of the vertical signal line 12 is taken in by the S/H and CDS circuit of a subsequent stage.
Then, at the timing of “t14”, a transfer pulse is inputted to the transfer transistor 22 for transferring the photoelectrons from the PD 10 to the FD node 16.
Thereafter, during a period including the timing of “t15”, the potential (light level) of the vertical signal line 12 is taken in again by the S/H and CDS circuit of the subsequent stage.
At the timing of “t16”, a reset pulse is inputted to reset the FD node 16 again.
Finally, at the timing of “t17”, the selection transistor 24 is turned off for restoration to the state at The S/H and CDS circuit serves as a circuit for obtaining the difference between two voltages successively taken in by itself, and holding that difference. In the operation described above, the S/H and CDS circuit obtains the difference between a value of the reset level and a value of the light level, and holds that difference as a signal level.
In the conventional solid-state image pickup device described above, it has been general that the selection transistor 24 is arranged on the side closer to the vertical signal line 12 than the amplification transistor 26, as shown in FIG. 4. The reason is in avoiding a voltage fall caused by lowering due to the threshold of the selection transistor 24 and an increase in resistance of the selection transistor 24.
On the other hand, it has also been general that the reset pulse is inputted during a period in which the selection transistor 24 is turned on, as shown in FIG. 5. The reason is presumably in such a common sense based on intuition that the transfer pulse and the reset pulse are preferably held in the same state (i.e., both the pulses are preferably inputted during a period in which the selection transistor 24 is turned on).
Meanwhile, one of the greatest advantages of a MOS type solid-state image pickup device is that the device operates at a voltage as low as that required for a surrounding LSI circuit.
Also, with the progress of the LSI technology, there is a tendency in recent years that the source voltage of LSI circuits lowers rapidly from 5 V to 3.3 V, then to 2.5 V, then to 1.8 V, and then to 1.3 V.
The MOS type solid-state image pickup device requires a voltage covering a source-follower operating voltage, a signal amplitude and a margin, and the signal amplitude is required to be 500 mV–1 V.
For those reasons, in the conventional MOS type solid-state image pickup device, a peripheral circuit such as a TG can be realized in match with the tendency toward a lower voltage, but the image pickup device itself has a difficulty in adaptation to a source voltage of not higher than 2.5 V because the voltage necessary for operating the pixel unit imposes an obstacle.